Informatics Publishing Limited

R. Zouaoui ¹, N. Khalfaoui ¹

Affiliations
1 Donetsk National Technical University, Artema 58, Donetsk 83001, UA

Abstract

In this paper new algorithm for the verification of the equivalence of the sequential digital circuits is proposed in which it allocated a combinational block and a block from the state of the elements represented by D-triggers. In the construction of evaluation functions using the task of modeling of a circuit intact or defective. This is done by breaking the feedback lines and using an iterative modeling of combinatorial equivalent. This algorithm is based on a new strategy for the evolution of simulated annealing. This approach uses an iterative improvement of the properties of the one input sequence. The algorithm is presented as an iterative process for improving the properties of a potential solution. The exact formal verification of ownership equivalence is a difficult mathematical problem, for this reason we have reformulated the opposite: we show the non-equivalence of scheme. Fault-free simulation of the digital circuits is used for the estimating the quality of the potential solutions. The effectiveness of the proposed algorithm is shown by its approbation on the ISCAS-89 benchmarks.

Keywords

Simulating Annealing, Genetic Algorithms, Verification of the Equivalence, Digital Circuits, Parallel Modeling.

Full Text

     

R. Zouaoui ¹, N. Khalfaoui ²

Affiliations
1 Department of Computer Technologies, ISET Nabeul, University Campus, 8000 Nabeul, TN
2 KEF Higher Institute of Computer, Rue Salah Ayach - 7119 LeKef, TN

Abstract

In this paper we propose a new algorithm for the construction of initialization sequences of synchronous sequential circuits. To resolve this problem we are encouraged to use a new optimization strategy which is "simulated annealing». For this we used the methods of technical analysis, the theory of Boolean functions, the switching circuits and their modeling logic, automata and evolutionary computation methods. Essentially in our work we use the model of synchronous sequential circuits, in which we allocate a combinational block and a block of the state of the elements represented by D-triggers. In the construction of evaluation functions we use the task of modeling a circuit intact or defective. This is done by breaking the return lines (feedback) and using a model of the equivalent iterative combinatorial. The advantage of this strategy, unlike the deterministic methods, is the ability of working with large circuits. The result of our work is summarized in two points: the study of simulated annealing algorithm to use to identify problems in the construction of initialization sequences and the development of a single-level algorithm for the simulation of annealing and construction of initialization sequences by checking their equivalence.

Keywords

Algorithm, Cost Function, Digital Circuits, Genetic Algorithm, Initialization Sequences, Sequential Circuits, Simulated Annealing, Synchronous Circuits.

Full Text